1. Field of the Invention
The present invention relates to a semiconductor device to which flip-chip bonding is applied, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, the flip-chip bonding is exploited as a technique for mounting with shorter wire and connection lengths in order to cope with the microchip (semiconductor element) with increased pins, finer pitch, and faster signal speed. The microchip used for flip-chip bonding contains, for example, electrode pads formed planimetrically and solder bumps formed on the electrode pads. On the other hand, the circuit substrate on which the microchip is to be mounted has electrode pads formed in positions corresponding to the electrode pads of the microchip. The flip-chip bonding is a method to place the electrode pads of the microchip and those of the circuit substrate so that they face each other, and bond the electrode pads of the microchip and those of the circuit substrate by heating and dissolving the solder bumps therebetween.
Normally, a flux paste is applied to the surface of the circuit substrate in order to reduce the oxide films on the solder bumps, after which the microchip is aligned and mounted on the circuit substrate. Subsequently, the solder bumps are heated and dissolved using a reflow oven so that the electrode pads of both sides are bonded, and thereafter the flux is cleaned. Then, sealing resin (underfill material) is filled between the circuit substrate and the microchip and cured. The semiconductor device exploiting the flip-chip bonding is thus manufactured. Further, for the flip-chip bonding, sealing resin having flux function, so-called no-flow underfill material, is also used so as to simplify the bonding process. The bonding process using the sealing resin with flux function omits the steps to clean the flux and filing the sealing resin, allowing process simplification and cost reduction.
Hereinafter, the bonding process using the sealing resin with flux function is explained with reference to FIGS. 12 to 14. First, as shown in FIG. 12, solder bumps 3 composed of a high melting point solder such as a Sn—Ag solder (melting point: 221° C.) are formed on electrode pads 2 of a microchip 1. On the other hand, on electrode pads 5 of a circuit substrate 4, on which the microchip 1 is to be mounted, low melting point solder layers 6 composed of Sn—Bi solder (melting point: 139° C.) and the like are formed. Sealing resin 7 with the flux function is then applied over the circuit substrate 4. Here, in general, the circuit substrate 4 exhibits warp of about 20 to 50 μm within the mounting area (15 to 20 mm of square).
Next, as shown in FIG. 13, the microchip 1 is absorbed and retained by a mounting tool 8. The mounting tool 8 is preheated at a temperature at which only the low melting point solder layers 6 melt (for example, 139° C. or higher and lower than 221° C.). After aligning the electrode pads 2 of the microchip 1 and the electrode pads 5 of the circuit substrate 4, the microchip 1 is pressed onto the circuit substrate 4 through over the sealing resin 7. While retaining this pressing state, the mounting tool 8 heats the sealing resin 7 and the low melting point solder layers 6. The flux facility of the sealing resin 7 activated by heating eliminates the oxidize film and foreign substance in the bonded interface, while only the low melting point solder layers 6 are dissolved and wetted up to the solder bumps 3. At this stage, the circuit substrate 4 is in parallel by the pressing force. The microchip 1 is thus tentatively bonded to the substrate 4.
Thereafter, the microchip 1 is released from the mounting tool 8. At this stage, the pressing force imposed on the microchip 1 is eliminated, so that the circuit substrate 4 is warped back as shown in FIG. 14. The low melting point solder layers 6 are still in the melting state immediately after the pressing force is released, so that they may be pulled apart as shown in FIG. 15, depending on the degree of warping back of the circuit substrate 4. Subsequently, the sealing resin 7 is cured and hardened, which causes disconnection in the parts where the low melting point solder layers 6 are pulled apart after the final connection process of heating and dissolving the solder bumps 3 is performed. Thus, the problem for the flip-chip bonding process using the sealing resin with flux function is the disconnection occurrence due to warp of the circuit substrate 4.
Further, in order to cope with even finer pitches and higher signal speeds of a microchip, application of copper wiring for lowering resistance and low dielectric constant insulating film (low-κ film) for reducing inter-wiring capacity is being proceeded. However, materials composing the low-κ film in general have a drawback of lower mechanical and adhesion strengths. Accordingly, in the flip-chip bonding process, the low-κ film itself or interface thereof are likely to cause cracking and exfoliation due to thermal stress caused by the thermal expansion coefficient difference between the microchip and the circuit substrate. In particular, use of zinc-free solders such as the Sn—Ag solder causes a large thermal stress during the solder bump ref lowing step, where cracking or exfoliation is likely to occur because of the low mechanical and adhesive strengths of the low-κ film.
Incidentally, varieties of proposals have been provided regarding the structure of the solder bump or the soldering method. For example, the Japanese Patent Laid-open Application No. Hei 10-294337 provides a bump electrode configuration composed of a high melting point solder metal layer, mid melting point solder metal layer, and low melting point solder layer formed in the order thereof from the side of the circuit substrate. This configuration allows lowering of the thermal stress based on the thermal expansion coefficient difference between the microchip and the circuit substrate in the bump electrodes, in such a manner that the high-strength high melting point solder metal layer is formed on the circuit substrate side. Such a bump configuration may contribute to lowering of the stress against the microchip, but is not effective enough against the disconnection due to the warping back of the circuit substrate.
The Japanese Patent Laid-open Application No. Hei 10-209626 provides a method to form solder layers on both ends of a pillar composed of a high melting point conductive material, to tentatively bond the solder layers on the both ends with a flux which provides adhesion to the electrodes pads of the microchip and the substrate, and to perform soldering by melting and solidifying the solder layers of the both ends. However, such a soldering method is not at all applicable to the flip-chip bonding of a microchip with increased number of pins. The Japanese Patent Laid-open Application. No. Hei 10-12659 presents a configuration that metal bumps provided on the microchip side and high melting point solder bumps provided on the circuit substrate side are bonded together through lower melting point layers. In such a bonding configuration, a satisfactory effect cannot be attained against the disconnection due to warping back of the circuit substrate, nor reduction of the stress can be expected.